The present disclosure relates to an interconnection apparatus, and more particularly to an interconnection apparatus which transfers data permitting a split transaction and a controlling method for an interconnection apparatus.
Usually, in order to transfer data from a certain module to a different module, a technique of connecting the modules to each other by a bus is used frequently. That one of the modules which leads data transfer is called master while the module which operates passively is called slave. The module which acts as the master typically is a processor. The module which acts as the slave typically is a memory.
In a system which includes a plurality of buses which are different in bus width or endian system, a bus bridge which carries out data conversion in accordance with the difference in bus width and so forth is provided. Associated buses are connected to the bus bridge to allow data transfer between the buses. The buses and bus bridge are also called interconnect.
In such a bus system as just described, the transfer efficiency can be improved by permitting a split transaction. The split transaction is to control, from among a series of actions or transactions for data transfer, requesting for data transfer and actual data transfer independently of each other. As a bus standard which permits a split transaction, the AXI (Advanced eXtensible Interface) bus and so forth are available.
In the case where a split transaction is permitted, the interconnect such as a bus bridge keeps transaction information relating to transfer between the master and the slave within a period within which the transfer remains unsettled or outstanding. Here, the unsettled signifies a state in which the requested data transfer remains incomplete. Further, the transaction information is information necessary for control of transfer of a response. For example, the transaction information includes a burst length or a burst number when burst transfer is carried out.
The necessity for the interconnect to keep transaction information in the split transaction is described. A bus system is assumed wherein two masters M1 and M2 and two slaves S1 and S2 are connected to an interconnect. It is assumed that, in this bus system, the master M1 issues a request A for requesting for data transfer to the slave S1 first and then the master M2 issues a request B for requesting for data transfer to the slave S2. Also it is assumed that the request A requests for burst transfer while the request B does not request for burst transfer. While the slaves S1 and S2 individually return a response in response to the corresponding request, the order in returning of such responses may not be the same as the order in issuance of the requests A and B. In such a case, in order to decide which one of the responses is to be transferred by burst transfer, the interconnect keeps transaction information corresponding to the requests within periods within which the transfers remain unsettled. The interconnect can control the data transfers appropriately by referring to the transaction information kept therein.
As a technique for keeping transaction information in an AXI bus, a bus system wherein a FIFO (First In First Out) system is provided for each transaction has been proposed and is disclosed, for example, in Japanese Patent Laid-Open No. 2008-41099. The number of such FIFO systems is greater than a maximum value of the number of permissible unsettled transfers. The interconnect stores transfer information corresponding to each request into a FIFO system corresponding to a transaction relating to the request. With the configuration described, when the interconnect reads out transaction information from any of the FIFO systems, there is no necessity to search for a corresponding transaction. Therefore, a readout process of the transaction information can be carried out at a high speed.